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(R)
9-Line SCSI Terminator
-DS21S07A Upgrade
IMP5 1 15
ISO 9001 Registered
DESCRIPTION
The IMP5115 SCSI terminator is part of IMP's family of high-performance, adaptive, non-linear mode SCSI products, which are designed to deliver true UltraSCSI performance in SCSI applications. The low voltage BiCMOS architecture employed in its design offers performance superior to older linear passive and active techniques. IMP's SCSI termination architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible -- typically 35MHz, which is 100 times faster than the older linear regulator/ terminator approach used by other manufacturers. Products using this older linear regulator approach have bandwidths which are dominated by the output capacitor and which are limited to 500KHz (see further discussion in the Functional Description section). This new architecture also eliminates the output compensation capacitor required in earlier terminator designs. Each is approved for use with SCSI-1, -2, -3, UltraSCSI and beyond -- providing the highest performance alternative available today. Another key improvement offered by the IMP5115 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as the use of improper cable lengths and impedances. Frequently, this situation is not controlled by the peripheral or host designer and, when problems occur, they are the first to be made aware of the problem. The IMP5115 architecture is much more tolerant of marginal system integrations. Recognizing the needs of portable and configurable peripherals, the IMP5115 has a TTL compatible sleep/disable mode. Quiescent current is typically less than 375A in this mode, while the output capacitance is also less than 3pF. The obvious advantage of extended battery life for portable systems is inherent in the product's sleep-mode feature. Additionally, the disable function permits factory-floor or production-line configurability, reducing inventory and product-line diversity costs. Field configurability can also be accomplished without physically removing components which, often times results in field returns due to mishandling. Reduced component count is also inherent in the IMP5115 architecture. Traditional termination techniques require large stabilization and transient protection capacitors of up to 20F in value and size. The IMP5115 architecture does not require these components, allowing all the cost savings associated with inventory, board space, assembly, reliability, and component costs.
KEY FEATURES
s ULTRA-FAST RESPONSE FOR FAST-20 SCSI APPLICATIONS s 35MHz CHANNEL BANDWIDTH s 3.5V OPERATION s LESS THAN 3pF OUTPUT CAPACITANCE s SLEEP-MODE CURRENT LESS THAN 375A s THERMALLY SELF LIMITING s NO EXTERNAL COMPENSATION CAPACITORS s IMPLEMENTS 8-BIT OR 16-BIT (WIDE) APPLICATIONS s COMPATIBLE WITH ACTIVE NEGATION DRIVERS (60mA / CHANNEL) s COMPATIBLE WITH PASSIVE AND ACTIVE TERMINATIONS s APPROVED FOR USE WITH SCSI 1, 2, 3 AND ULTRA SCSI s HOT SWAP COMPATIBLE s PIN-FOR-PIN COMPATIBLE WITH DS21S07A / 2105
PRODUCT HIGHLIGHT
RE C E I V I N G WAV E F O R M - 20MHZ
DR I V I N G WAV E F O R M - 20MH Z
Receiver 1 Meter, AWG 28 IMP5115 LX5268
Driver IMP5115 LX5268
PACKAGE ORDER INFORMATION TJ (C) 0 to 125
D Plastic SOIC 16-pin
IMP5115CD
DW Plastic SOWB 16-pin
IMP5115CDW
PWP Plastic TSSOP 20-pin, Power
IMP5115CPWP
Note: All surface-mount packages are available in Tape & Reel. Append the letter "T" to part number. (i.e. IMP5115CDWT)
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ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE PIN OUTS
16 2 3 4 5 6 7 8 15 14 13 12 11 10 9
Continuous Termination Voltage .......................................................................... E R M I N A T O TERM POWER U L T R A 9 - C H A N N E L S C S I T 10V R D0 Continuous Output Voltage Range ............................................................... 0 to 5.5V D1 Continuous Disable Voltage Range .............................................................. 0 to 5.5V D2 Operating Junction Temperature ........................................................... 0C to 125C D3 Storage Temperature Range .............................................................. -65C to +150C D4 Solder Temperature (Soldering, 10 seconds) .................................................... 300C N.C.
Note 1. Exceeding these ratings could cause damage to the device.
GND
DISABLE N.C. D8 D7 D6 D5 N.C. N.C.
THERMAL DATA
D PACKAGE:
D PACKAGE (Top View)
THERMAL RESISTANCE-JUNCTION TO AMBIENT, QJA ...................... 120C/W
DW PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, QJA ........................ 95C/W
PWP PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, QJA ....................... 139C/W
Junction Temperature Calculation: TJ = TA + (PD x JA). The JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow.
TERM POWER D0 D1 D2 D3 D4 N.C. GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
DISABLE N.C. N.C. D8 D7 D6 D5 N.C.
DW PACKAGE (Top View)
TERM POWER HEATSINK/GND D0 D1 D2 D3 D4 HEATSINK/GND N.C. GND
20 2 3 4 5 6 7 8 9 10 19 18 17 16 15 14 13 12 11
DISABLE N.C. HEATSINK/GND N.C. D8 D7 D6 D5 HEATSINK/GND N.C.
PWP PACKAGE (Top View)
RECOMMENDED OPERATING CONDITIONS (Note 2) Parameter
Termination Voltage High Level Enable Input Voltage Low Level Disable Input Voltage Operating Virtual Junction Temperature Range IMP5115C Note 2. Range over which the device is functional.
Symbol
VTERM VIH VIL
Recommended Operating Conditions Min. Typ. Max.
3.5 2 0 0 5.5 VTERM 0.8 125
Units
V V V C
ELECTRICAL CHARACTERISTICS
Term Power = 4.75V unless otherwise specified. Unless otherwise specified, these specifications apply at the recommended operating ambient temperature of TA = 25C. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.
Parameter
Output High Voltage TermPwr Supply Current
Symbol
VOUT ICC
Test Conditions
Min.
2.65
IMP5115 Typ. Max. Units
2.85 6 215 375 -23 10 -90 10 3 35 60 9 225 -24 V mA mA A mA nA A nA pF MHz mA
Output Current Disable Input Current Output Leakage Current Capacitance in Disabled Mode Channel Bandwidth Termination Sink Current, per Channel
IOUT IIN IOL COUT BW ISINK
All data lines = open All data lines = 0.5V Disable Pin < 0.8V VOUT = 0.5V Disable Pin = 4.75V Disable Pin = 0V Disable Pin = < 0.8V, VO = 0.5V VOUT = 0V, frequency = 1MHz VOUT = 4V
-21
2
BLOCK DIAGRAM
TERM POWER
THERMAL LIMITING CIRCUIT
CURRENT BIASING CIRCUIT
24mA CURRENT LIMITING CIRCUIT
DATA OUTPUT PIN DB(0)
2.85V
DISABLE PIN 1.4V 1 OF 9 CHANNELS
FUNCTIONAL DESCRIPTION
24mA on assertion and by imposing 2.85V on deassertion. In Cable transmission theory suggests to optimize signal speed and order to disable the device, the Disable pin must be driven logic quality, the termination should act both as an ideal voltage Low. This mode of operation places the device in a sleep state reference when the line is released (deasserted) and as an ideal where a meager 375A of quiescent current is consumed. current source when the line is active (asserted). Common active Additionally, all outputs are in a Hi-Z terminators, which consist of Linear Regulators in series with resistors POWER UP / POWER DOWN FUNCTION TABLE (impedance) state. Sleep mode can be used for power conservation or to (typically 110), are a compromise. completely eliminate the terminator As the line voltage increases, the Disable Quiescent Outputs from the SCSI chain. In the second amount of current decreases linearly by IMP5115 Current case, termination node capacitance is the equation V = I * R. The H Enabled 6mA important to consider. The terminator IMP5115, with its unique new will appear as a parasitic distributed architecture applies the maximum L HI Z 375A capacitance on the line, which can amount of current regardless of line Open Enabled 6mA detract from bus performance. For this voltage until the termination high reason, the IMP5115 has been optithreshold (2.85V) is reached. mized to have only 3pF of capacitance per output in the sleep Acting as a near ideal line terminator, the IMP5115 closely state. reproduces the optimum case when the device is enabled. To An additional feature of the IMP5115 is its compatibility with enable the device the Disable Pin must be pulled Logic High or active negation drivers. The device handles up to 60mA of sink left open. During this mode of operation, quiescent current is current for drivers which exceed the 2.85V output high. 6mA and the device will respond to line demands by delivering
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PACKAGE DIMENSIONS
U LT R A 9 - CH A N N E L S C S I T E R M I N AT O R
D
16-Pin Plastic S.O.I.C.
16
A
9
B
1 8
P
F
G
D L C M
SEATING PLANE
K
J
DIM A B C D F G J K L M P
MILLIMETERS MIN MAX 9.78 10.01 3.81 4.01 1.35 1.75 0.35 0.46 0.51 0.77 1.27 BSC 0.19 0.25 0.10 0.25 4.82 5.21 0 8 5.79 6.20
INCHES MIN MAX 0.385 0.394 0.150 0.158 0.053 0.069 0.014 0.018 0.020 0.030 0.050 BSC 0.007 0.010 0.004 0.010 0.189 0.205 0 8 0.228 0.244
D W
16-Pin Plastic (SOWB) Widebody S.O.I.C.
16
A
9
B
1 8
P
F
G
D L C M
SEATING PLANE
K
MILLIMETERS DIM MIN MAX A -- 10.67 B 7.49 7.75 C 2.35 2.65 D 0.25 0.46 F 0.64 0.89 G 1.27 BSC J 0.23 0.32 K 0.10 0.30 L 8.13 8.64 M 0 8 P 10.26 10.65
INCHES MIN MAX -- 0.420 0.295 0.305 0.093 0.104 0.010 0.018 0.025 0.035 0.050 BSC 0.009 0.013 0.004 0.012 0.320 0.340 0 8 0.404 0.419
J
PWP 20-Pin Thin Small Shrink Outline (TSSOP)
321
EP
D F AH
E
(R)
ISO 9001 Registered
SEATING PLANE
B
G
L
C
M
DIM A B C D E F G H L M P
MILLIMETERS MIN MAX -- 0.90 0.18 0.30 0.90 0.180 6.40 6.60 4.30 4.48 0.65 BSC 0.05 0.15 -- 1.10 0.50 0.70 0 8 6.25 6.50
INCHES MIN MAX -- 0.354 0.0071 0.0118 0.0035 0.0071 0.252 0.260 0.169 0.176 0.025 BSC 0.002 0.005 -- 0.0433 0.020 0.028 0 8 0.246 0.256
IMP, Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134 Tel: 408.432.9100 Main Tel: 800.438.3722 Fax: 408.434.0335 Fax-on-Demand: 800.249.1614 (USA) Fax-on-Demand: 303.575.6156 (International) e-mail: info@impinc.com http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc. All other company and product names are trademarks of their respective owners.
(c) 1997 IMP, Inc. Printed in USA Part No.: IMP5115 Document Number: IMP5115-01-9/97
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